The present invention relates to programming means for sequentially producing groups of data to be transmitted to an arithmetic logic unit to cause such unit to execute selected instructions upon arithmetic data processed therein.
In prior art systems, a relatively large main programming memory contains blocks of data, each block being associated with a particular instruction to be executed by the arithmetic logic unit. An address memory addresses a selected block of data within the programming memory and causes such selected block of data to be sequentially transmitted to the arithmetic logic unit. Since major portions of the data in each different instruction block are the same with respect to corresponding data in the other blocks, and since only minor portions of the data within each block are unique to particular instructions to be executed, this prior art approach is extremely wasteful of storage capacity of the main programming memory. One approach with respect to reducing such storage capacity is to employ subroutining techniques known in the art. Such techniques, however, rule out a common first control memory subcell so that on balance this approach does not minimize main control memory requirements.
It has thus been desirable to reduce the main programming memory requirements and yet maintain a high speed single level microprogramming address mapping system. The approach in the present invention is based upon the fact that a class of computer instructions such as add, subtract, exclusive OR, AND, and the like are implemented in controlled sequences which only differ in limited respects in accordance with the particular instruction being executed. In other words, major portions of the data within each block do not differ from corresponding data in other blocks, so that a great deal of redundancy, which results in waste of storage capacity exists. In accordance with the present invention, such storage capacity is drastically reduced, and at the same time the speed of operation is not sacrificed and is substantially the same as the operating speed of the prior art approach which employs a large main microprogramming memory. There has been a long felt need in the countermeasures field to drastically reduce the requisite storage capacity of the microprogramming memory and thus the total memory requirements of the system, to minimize memory device volume, while at the same time maintaining extremely high operating speeds.